Embodiments of the inventive concept are directed to an integrated circuit, and more particularly, to a computer-implemented method and a computing system for designing an integrated circuit by considering process variations of wires.
An integrated circuit can be designed based on standard cells. Specifically, a layout of an integrated circuit may be generated by placing standard cells that define the integrated circuit and routing the placed standard cells. As a semiconductor device is miniaturized, the size of patterns included in a layout gradually decreases, and accordingly, minute differences between the size of a designed pattern and the size of a pattern implemented by hardware causes degradation in yield of the integrated circuit. Wire process variations include resistance/capacitance variations in metal layers or vias. When the resistance of a metal layer is greater than a nominal value, a clock delay may increase, and accordingly, timing violations can occur. A conventional parasitic component description file includes resistance sensitivity and capacitance sensitivity for each node. As a result, the size of the parasitic component description file is very large, and in a timing analysis operation, the complexity of and time required for a calculation can greatly increase. In particular, due to wire process variations corresponding to a back-end-of-line (BEOL), a delay through a timing path that includes the wire can increase, and thus, a timing constraint violation may occur in the timing path.